The demand for advanced multimedia features are pushing device manufacturers to integrate more advanced peripherals such as multi-megapixel cameras and larger screens. Integrating these capabilities into next-generation devices brings new challenges to the industry in terms of power, time-to-market and overall system costs.
To address these challenges, the Mobile Industry Processor Interface (MIPI®) Alliance defines and promotes open interface specifications, such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI), which all use the MIPI D-PHY.
MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.
The D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for high-Speed data traffic while low power functions are mostly used for control. In HS mode, the low swing differential signal is able to support data transfers from 80 Mbps to 1.5 Gbps. In LP mode all wires operate as a single-ended line capable of supporting 10 Mbps asynchronous data communications. The D-PHY is a complete PHY, silicon-proven at multiple foundries.
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- The DesignWare MIPI D-PHY IP provides a high-reliability, high-speed differential interface, reducing line count and minimizing cable wires and EMI shielding requirements.
- Programmable 1, 2 or 4 Data Lane Configuration.
- Supports ultra low power mode, high-speed mode, and escape mode
- Supports one clock lane and up to four data lanes
- Testability for Tx, Rx, and PLL
- 80 Mbps to 2.5Gbps data rate in high-speed mode
- 10 Mbps data rate in low-power mode
- Supports High-speed mode in Forwarding communication
- PHY can be configured as a master or slave
- One byte buffer is housed inside the core for both data-out and data-in paths
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Available in various foundry processes
- Fully synchronous design
- Active low Asynchronous reset
- Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests
- Low-power escape modes and ultra-low-power state modes
- Shutdown mode
- SCAN and loopback BIST modes
- GDSII and LVS Netlist
- RTL code
- Synthesis environment/scripts
- LIB & LEF
- Process Specific Integration Guide
- Timing Models (LIB) and Physical Abstract Models (LEF)
- Physical Verification Report
- Consumer Electronics
- VR & AR
- CSI-2 Host & Device
- DSI Host & Device