You are here:
MIPI DPHY & LVDS Transmit Combo on GF55LPe
This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications. This IP supports up to 1.5Gbps for both MIPI and LVDS data rate. This IP can be applied to OpenLDI v0.95 also. This IP includes two PLLs. One is a generic PLL for MIPI clock generation, and the other is an X8/X7 multiplier PLL for serial clock generation.
查看 MIPI DPHY & LVDS Transmit Combo on GF55LPe 详细介绍：
- 查看 MIPI DPHY & LVDS Transmit Combo on GF55LPe 完整数据手册
- 联系 MIPI DPHY & LVDS Transmit Combo on GF55LPe 供应商
Block Diagram of the MIPI DPHY & LVDS Transmit Combo on GF55LPe
MIPI D-PHY1.2/LVDS TX IP
- MIPI D-PHY Tx and Rx SMIC 40LL supporting LVDS and HiSPi
- MIPI D-PHY Tx and Rx SMIC 55LL supporting LVDS and HiSPi
- MIPI D-PHY Tx and Rx TSMC 55 GP/LP supporting LVDS and HiSPi
- MIPI D-PHY Tx and Rx TSMC 110G supporting LVDS and HiSPi
- MIPI D-PHY Tx and Rx SMIC 90LL/G supporting LVDS and HiDPi
- MIPI D-PHY Tx and Rx GF 110TS supporting LVDS and HiSPi