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MIPI DPHY & LVDS Transmit Combo on GF55LPe
This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications. This IP supports up to 1.5Gbps for both MIPI and LVDS data rate. This IP can be applied to OpenLDI v0.95 also. This IP includes two PLLs. One is a generic PLL for MIPI clock generation, and the other is an X8/X7 multiplier PLL for serial clock generation.
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Block Diagram of the MIPI DPHY & LVDS Transmit Combo on GF55LPe
MIPI D-PHY1.2/LVDS TX IP
- LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL
- MIPI D-PHY Tx and Rx PHY and Controller in TSMC 40LP supporting LVDS and HiSPi
- MIPI D-PHY Tx and Rx PHY&Controller in TSMC 110G supporting LVDS and HiSPi
- MIPI D-PHY Tx and Rx PHY and Controller SMIC 110/130G supporting LVDS and HiSPi
- MIPI D-PHY Tx and Rx PHY&Controller in SMIC 90LL/G supporting LVDS and HiDPi
- MIPI D-PHY Tx and Rx PHY & Controller GF 110TS supporting LVDS and HiSPi