MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
In D-PHY mode, The IP can be configured as a MIPI Master optimized for display (DSI) applications. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
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Block Diagram of the MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
mipi IP
- MIPI CSI-2 Controller Core V2
- MIPI CSI-2 Controller Core
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
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