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MIPI CSI-2 Transmitter IP Core
CSI-2 (Camera Serial Interface) transmitter IP core is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs packing in form of long packets, and Short packets, and sends them via PPI interface to the Host processor. Designed for use in portable electronic devices such as media players, mobile phones, and personal assistant devices, the CSI-2 Transmitter IP core is fully compliant to MIPI Alliance's CSI standard, as well as to AMBA's AHB specification.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
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MIPI CSI-2 Transmitter IP
- MIPI CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY CSI-2 TX+ in TSMC 28nm HPC+
- MIPI C-PHY CSI-2 TX+ for TSMC 40ULP
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard