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Memory & Logic Library
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Memory & Logic Library IP Core

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Memory & Logic Library IP Listing

5132 IP Cores (3641 - 3680)

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8 track thick oxide standard cell library at TSMC 130 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)

TSMC 130 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the use of a patented flip flop.

3641
6 track High Density standard cell library at TSMC 180 nm

TSMC 180 G, SESAME HD provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells.

3642
High Density Dual Port SRAM Compiler - TSMC 40 nm CLN40G

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. ...

3643
High Density Via Programmable ROM Compiler - Samsung 28 nm CMOS28LP

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. ...

3644
High Density Single Port SRAM Compiler - Samsung 45 nm CMOS11LP

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. ...

3645
High Density Single Port SRAM Compiler - Samsung 45 nm CMOS11LP

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. ...

3646
High Density Dual Port SRAM Compiler - Samsung 45 nm CMOS11LP

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. ...

3647
SC12MC Standard Cell Library - TSMC 28 nm CLN28HPM

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

3648
SC9MC Supplemental Cell Kit - TSMC 40 nm CLN40LP

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

3649
SC9MC Supplemental Cell Kit - TSMC 40 nm CLN40LP

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

3650
High Density Single Port Reg File Compiler - TSMC 65 nm CLN65LP

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. ...

3651
High Density Two Port Reg File Compiler - TSMC 65 nm CLN65LP

ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. ...

3652
SC12MC Standard Cell Library - UMC 28 nm L28HLP

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering ...

3653
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell

VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell (06) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, and input buffer with pull-up only cells. This library ...

3654
VeriSilicon UMC 0.18μm CF I/O

VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II logic process. This library supports inline I/O pads. ...

3655
VeriSilicon UMC 0.18μm CF I/O

VeriSilicon UMC 0.18μm CF I/O Cell (01) Library developed by VeriSilicon is optimized for UMC 0.18μm 1.8v/3.3v 1P6M Generic II logic process. This library supports inline I/O pads. ...

3656
SMIC 0.13um 9 track High Density Standard Cell Library - HVT,1.2v operating voltage

SMIC 0.13um 9T HVT High-Density Standard Cell Library

3657
SMIC 0.18um 3.3V Standard Cell Library,3.3v operating voltage

SMIC 0.18um 3.3V Standard Cell Library

3658
Silterra 0.11um High Density Single-Port Register File Compiler

VeriSilicon SMSB 0.11um Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor Manufacturing Corporation (SMSB) 0.11um 1P8M 1.8V/3.3V process can flexibly generate ...

3659
Wide-range LVDS Video Interface

Flexible video serializer capable of transmitting 18bit, 24bit, and 30bit video data with embedded sync and control over four or five LVDS outputs. Programmable emphasis control on the LVDS ...

3660
Wide-range LVDS Video Interface

Flexible video deserializer capable of receiving 18bit, 24bit, and 30bit video data with embedded sync and control carried over four or five serial LVDS compliant inputs. Deserialized data is ...

3661
ROM Compiler IP, UMC 0.25um process

UMC 0.25um Logic process synchronous VIA2 programmed ROM memory compiler.

3662
ROM Compiler IP, UMC 40nm LP process

UMC 40nm LP Via1 ROM compiler with Sleep mode.

3663
Standard Cell (Generic) Library IP, HVT, 7 tracks, UMC 28nm HLP process

UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).

3664
Standard Cell (Generic) Library IP, UMC 0.13um LL process

UMC 0.13um LL Logic/FSG process high density Core Cell Library.

3665
Via Programmable ROM - TSMC 55nm GP (CLN55GP)

Dolphin Technology maintains a broad IP portfolio of Memory Compilers, Specialty Memory and Memory Test & Repair (Memory BIST), providing SoC designers with solutions optimized for low power, ...

3666
Low Leakage - Ultra High Speed One Port Register File (1 Port RF) Compiler with Column Redundancy Option - TSMC 28nm 28HP (CLN28HP)

Dolphin Technology maintains a broad IP portfolio of Memory Compilers, Specialty Memory and Memory Test & Repair (Memory BIST), providing SoC designers with solutions optimized for low power, ...

3667
ONFI 4.1 I/O Pad Set

The ONFI 4.1 library provides the combo driver / receiver cells, the ODT / driver impedance calibration cell, and the voltage reference cell to support both single-ended and differential ONFI ...

3668
Ultra High Density and Ultra Low Power 7-track Standard cell library - TSMC 90nm GT (CLN90GT)

Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 3500 fully customizable ...

3669
Embedded MTP (Multi-Time Programmable) IP, 1.8V/5V BCD

eMemory's NeoEE carries out electronic program-/erase- operations for 16k-bit (maximum) memory density and functions as a true rewritable memory technology, allowing up to 111K P/E cycling with ...

3670
Secured 1553 FPGA IP Core

The world’s first secured MIL-STD-1553B FPGA IP Core. Based on the popular BRM1553D , the secured 1553 IP core enables real-time detection and prevention of various cyber attacks on the MIL-STD-1553B ...

3671
512bit Efuse with parallel input and parallel output

Program Voltage:2.5V, Program Temperature:10~40 degrees, 512bit Efuse with parallel input and parallel output

3672
SMIC 55nm High-Speed RVT Standard Library for Power Management Kit.

SMIC 55nm High-Speed RVT Standard Library for Power Management Kit.

3673
SMIC 65nm LL(LVt) ECO cells compatible with HS standard cell library.

SMIC 65nm LL(LVt) ECO cells compatible with HS standard cell library.

3674
SMIC 130nm G SSTL2 and LVTTL combo I/O library

SMIC 0.13um SSTL2 and LVTTL combo I/O library; SMIC 0.13um Logic 1P8M Salicide 1.2V/3.3V Process; Suitable for 6,7 and 8 layers application; Compatible with SP013D3

3675
SMIC 130nm (HVt) high density standard cell library.

SMIC 130nm (HVt) high density standard cell library.

3676
LVDS IO and Transeiver

400Mbps – 2.5Gbps per-lane data rate LVDS transceiver ; Support up to 16 transmitter and receiver lanes with shared PMU ; Minimum 280mV output swing for low EMI operation ; -55 DegC – 150 ...

3677
This fifo access external OnChip dual port memory to store data.

This is fully configurable FIFO with configurable Depth, Configurable width. Fifo Storage Memory is implemented by External Dual Port Memory. It has option to select CDC mythology and CDC ...

3678
This fifo uses external onchip single port memory to store data.

This is fully configurable FIFO with configurable Depth, Configurable width. Fifo Storage Memory is implemented by External Single Port Memory without any drop in Bandwidth on any port. It ...

3679
This is capable to transferring data even when internal or exteral clock swings and overlaps each other

This is fully configurable Elastic Biffer with configurable Depth, Configurable width. Internal Storage Memory is implemented by Registers. It has internal CDC methodology which make it possible ...

3680

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