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Memory & Logic Library
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Memory & Logic Library IP Listing

4714 IP Cores (3641 - 3680)

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LVDS/FPD 链路 IP，在 GF 65/55LPe 中经过硅验证

这个PHY IP的低压差分信号（LVDS）发射器，这个IP有20条通道（4 x 4D1C）的LVDS驱动器，每通道1.5Gbps的数据速率。串行和并行数据在LVDS模式下分为4个通道；并行数据的每个通道的...

3641
LVDS/FPD 链路 IP，在 GF 28LPe 中经过硅验证

这个用于LVDS发射器的物理层IP，由20车道（4 x 4D1C）LVDS接收器组成，并支持高达1.5Gbps的数据速率。这个IP在LVDS模式下，串行数据和并行数据都被组织成4个通道，每个通道7位宽。...

3642
V-by-One Tx IP，在 SMIC 40LL 中经过硅验证

V-by-One HS技术是针对基于设备内部连接的视频信号的高速数据传输。V-by-One®HS标准定义了开发Rx和Tx标准。这个PHY IP支持4Gbps/通道的传输速率，并为Tx和Rx提供了8通道和16通道的...

3643
LVDS Rx IP，在 GF 28LPe 中经过硅验证

这个用于LVDS接收器的物理层IP，由20车道（4 x 4D1C）LVDS接收器组成，并支持高达1.5Gbps的数据速率。这个IP的输入时钟为25MHz到150MHz，其序列化器高度集成功能完善，不需要添加...

3644
LVDS/ MIPI Combo PHY IP, Silicon Proven in SMIC 40LL

The MIPI-LVDS Combo Tx IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can be easily fabricated and implemented in a GVI, ...

3645
IGALVDT11A, TSMC CLN28HPC+/HPC/HPM LVDS RX PHY [8ch]

The IGALVDT11A is a TSMC CLN28HPC+/HPC/HPM 8-channel LVDS receiver PHY, which is used mainly in baseband IC and RFIC communication. An internal deskew PLL (IGAPLLT12A) is included inside the ...

3646
IGALVDT13A, TSMC 28nm HPC+ LVDS TX+RX I/O

IGALVDT13A, TSMC 28nm HPC+ LVDS TX+RX I/O

3647
IGALVDT14A, TSMC CLN28HPC+ LVDS RX and CMOS Combo I/O

IGALVDT14A contains a receiver (RX) for LVDS interface and bi-derectional double CMOS. It supports the data rate up to 500Mbps. There is one macro inside this IP, 1 channel RX receiver IO. The ...

3648
A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell

Key attributes of our TSMC 65nm IO library include dual independent IO supply rails (1.0V-3.3V & 3.3V) and power-on-control (POC) to place IOs in a low-power HiZ state during power-down. The ...

3649
A radiation-hardened 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell

Key attributes of the 130nm IO library include an extended operational temperature range (-55°C to 200°C), sleep retention, and a built-in power regulation PMOS device for core VDD. The GPIO ...

3650
Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings

Certus is pleased to offer I2C open-drain IOs across multiple process technologies. The Certus I2C IO can support external supplies of 1.8V, 3.3V and 5V at Fast Mode (400Kbps) and Fast Mode+ ...

3651
High-voltage solutions in baseline TSMC and GlobalFoundries technology

Certus is pleased to offer High-voltage ESD solutions across multiple baseline technologies. Distinguishing Certus is our ability to provide high-voltage ESD solutions achieving 10V, 15V and ...

3652
1.0-3.3V GPIO With I2C Open Drain And 3.3V & 5V Analog Cells in TSMC 65nm

A TSMC 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain cells, 3.3V & 5V analog cells, OTP program cell & associated ESD Key attributes of ...

3653
LVDS IO Pad Set

The LVDS I/O is a three-module design (input, output and reference block). The LDP_OU_675_25V_T is a 2GBit/s LVDS Driver, LDP_IN_675_25V_DN is a 2GBit/s LVDS Receiver and the LDP_RE_000_25V ...

3654
MIPI D-PHY/LVDS combo Transmitter 700Mbps 8-Lane

The CL12661H8T1JM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12661H8T1JM2JIP is designed to support data rate in excess of maximum 700Mbps ...

3655
1.8V Secondary Oxide LVDS combo pad - TSMC 5nm 5FF

Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

3656
1.8V Secondary Oxide LVDS pad - TSMC 6nm 6FF

Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

3657
1.8V Secondary Oxide LVDS pad - TSMC 22nm 22ULP,ULL

Dolphin Technology's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR4/3/2, LPDDR3/2, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and ...

3658
1.8V Secondary Oxide LVDS pad - TSMC 28nm 28HP,HPL,LP,ULP,HPC,HPC+,HPM

Dolphin Technology's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR4/3/2, LPDDR3/2, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and ...

3659
1.8V Secondary Oxide LVDS & LVPECL I/O Combo Pad - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF

Dolphin Technology's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR4/3/2, LPDDR3/2, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and ...

3660
1.8V Secondary Oxide LVDS pad - TSMC 7nm 7FF,FF+

Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

3661
1.8V Secondary Oxide LVDS combo pad - TSMC 4nm 4FF/4P

Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

3662
2.5V Secondary Oxide LVDS pad - TSMC 40nm 40G,LP,LP_eF,ULP,ULP_eF

Dolphin's hardened DDR2/3/4 SDRAM PHY and LPDDR2/3 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 3.1 specification, and features ...

3663
1.8V Secondary Oxide LVDS combo pad - TSMC 3nm

Dolphin's interface IP for standard I/O and specialty I/O delivers ultra high performance for DDR1/2/3/4, LPDDR2/3, DDR PHY, LVDS, LVPECL, I2C, PCI, SerDes, Xaui Ethernet, SPI4.2 and more.

3664
LVDS IO in SMIC 28HKC+, upto 1.6Gbps

LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V power, based on 28nm HK and 40nm LL process. ...

3665
LVDS IO in SMIC 40NLL, upto 800Mbps

LVDS IO can be applied for various die-to-die interface communication. Brite LVDS IO libraries can support data rate up to 2000Mbps with 2.5V and 1.8V power, based on 28nm HK and 40nm LL process. ...

3666
500Mbps LVDS IP library

180TSMC_LVDS_10 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Transceiver LVDS driver (RX_TX_LVDS); • Reference current/voltage ...

3667
200 Mbps LVDS IP library

055TSMC_LVDS_03 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reference current/voltage generators (RS_TOP). The RS_TOP block is ...

3668
Library of LVDS Ios cells in SMIC 130nm~28nm

This IP is a total solution for LVDS applications, including LVDS transmitter I/O, receiver I/O, common block and power/ground I/O. LVDS transmitter and receiver support 1.2Gbps maximum data-rate. ...

3669
Library of LVDS Ios cells in HHGrace 130nm~55nm

This IP is a total solution for LVDS applications, including LVDS transmitter I/O, receiver I/O, common block and power/ground I/O. LVDS transmitter and receiver support 1.2Gbps maximum data-rate. ...

3670
Library of LVDS Ios cells in HLMC 28nm

This IP is a total solution for LVDS applications, including LVDS transmitter I/O, receiver I/O, common block and power/ground I/O. LVDS transmitter and receiver support 1.2Gbps maximum data-rate. ...

3671
Library of LVDS Ios cells in TSMC 180nm~22nm

This IP is a total solution for LVDS applications, including LVDS transmitter I/O, receiver I/O, common block and power/ground I/O. LVDS transmitter and receiver support 1.2Gbps maximum data-rate. ...

3672
1.25 Gbps LVDS IPs library

028TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reduced range link receiver LVDS driver (RX_LVDS_R); • Transceiver ...

3673
1.25 Gbps LVDS IPs library

040TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Reference current/voltage source (LVDS_RS); • Reference current/voltage ...

3674
Up to 400 Mbps DDR LVDS receiver

130GF_LVDS_01 is a LVDS receiver with data rate up to 400 Mbps (DDR mode). The LVDS receiver converts input LVDS signal to differential CMOS 1.5V standard and transmits it through the OUTP and ...

3675
RF Transceiver SMIC 55nm

AGP1322 RF Transceiver IP采用SMIC55nm工艺，应用于NB_IOT射频信号收发，兼容3GPP R14 NB_IOT标准，适用bands1, 2, 3，5, 8, 12, 13, 17, 18, 19,20, 26, 28，66频段。IP采用低...

3676
High-speed ultra-low noise LVDS Driver

Seamless Microsystems’ (SMI) SMLVDS28 is a silicon-proven LVDS I/O driver operating at 2.4 GHz in TSMC 28nm HPM process. Using a core supply voltage of 0.9V and an IO supply of 1.8V, the LVDS ...

3677
High-speed ultra-low noise LVDS Driver

Seamless Microsystems’ (SMI) SMLVDS55 is an LVDS I/O driver operating at 2.4 GHz in TSMC 55nm ULP process. Using a core supply voltage of 1.2V and an IO supply of 2.5V, the LVDS driver achieves ...

3678
LVDS transceiver IP

The LVDS transceiver IP is a SERDES pair that clearly interprets 12–bit parallel bus into serial stream. This serial stream clarifies the move of 12-bit or less bus over PCB finds and cables ...

3679
Mini-LVDS TX and RX PHY

The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process. It is suitable for the interface between the timing controller and column drivers.

3680

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