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Silicon IP Catalog
Memory Controller & PHY
> Page 7

Memory Controller & PHY IP Core

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Memory Controller & PHY IP Listing

1051 IP Cores (281 - 320)

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搜索特定的IP？点击此处

Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Command/address block of 1:2 DDR2-PHY ; 0.11um HS/AE (AL Advanced Enhancement) Logic Process

281
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

282
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process

283
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process

284
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process

285
DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

DDR2-PHY compensation block, BOAC; UMC 0.13um HS/FSG process

286
DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

DDR2-PHY compensation block, BOAC; UMC 90nm SP/RVT Low-K Logic process

287
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process

DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process

288
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process

289
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

290
DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

DDR2/MDDR PHY Data block ; UMC 65nm 1.0V with 2.5V device SP/RVT LowK Logic Process

291
DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

DDR2/MDDR Combo PHY data block ; UMC 55nm SP process with 2.5V device

292
DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

DDR2/MDDR Combo Data Block ; 0.13um Logic HS/FSG Logic Process

293
DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

DDR2/DDR1/MDDR Combo Data Block ; UMC 65nm LP/RVT LowK Logic Process

294
Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

295
1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

296
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process

297
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process

298
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process

299
DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY Command/Address block; UMC 90nm SP/RVT Lowk Process

300
DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

DDR2 PHY Data Block ;UMC 0.13um Logic HS/FSG Process

301
DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process

DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process

302
DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

DDR2-PHY data block with BOAC IO; UMC 90nm SP/RVT Lowk Logic Process

303
DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

DDR2-PHY data block; UMC 90nm SP/RVT Lowk Process

304
DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

DDR2/3 Combo Command /Address Block (with 2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Process

305
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device

306
DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

307
UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage

UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage

308
DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage

DDR23 COMBO PHY CMD/ADDR BLOCK ; UMC 40LP/RVT LowK Logic Process with 2.5V device for 2 layer PCB board usage

309
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

310
Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

Command/Address Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

311
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

312
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.

313
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process

314
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process

315
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

316
DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

317
DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess

318
DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device

319
Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

320

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