The RS-FEC Decoder IP is a highly optimized Reed Solomon Decoder solution designed for the IEEE 802.3bj standard.
The Reed Solomon codeword can be fed partially parallelized to the Decoder IP. The factor of parallelism can be chosen by the user. Additionally a fully pipelined architecture makes the IP suitable for high speed applications.
- IEEE 802.3bj compliant
- Fully pipelined architecture
- Parallelized Galois Field Inputs
- Parallelized Syndrome Calculation
- Erasure Decoding optional available
- Solving Key equation with modified euclid algorithm
- Fully pipelined and parallelized Chien-Forney error calculation
- Parallel output stream
- Optimized compile options targeted for ASIC and FPGA applications
Block Diagram of the IEEE802.3bj RS-FEC Decoder for 100Gb/s Application