i3c slave controller scl clock only configure user registers no cpu host required IP core / Semiconductor IP / Silicon IP

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I3c slave controller scl clock only configure user registers no cpu host required IP Listing

5 IP Cores

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I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface

The I2C Controller IP Core implements an I2C Slave Controller, with a user parameterized Register Array or Memory (i.e SRAM / FIFO) or any Peripheral connecting on an AHB / APB / AXI / Avalon ...

1
I2C Slave with APB Master Bridge (I2C2APB)

The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

2
I2C Slave with AXI Master Bridge (I2C2AXI4)

The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

3
I2C Slave with AHB Master Bridge (I2C2AHB)

The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & control registers (and thus no local host ...

4
AXI4 to/from AXI4-Stream Scatter-Gather DMA

The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master ...

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