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I3C Slave Controller, SCL Clock only, Configure User Registers, no CPU Host Required
The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no free running clock. The DB-I3C-S-SCL-CLK-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers.
The DB-I3C-S-SCL-CLK-REG builds on Digital Blocks DB-I2C-S-SCL-CLK Controller and additionally supports I2C Master Slave-Transmit and Slave-Receive .
The DB-I3C-S-SCL-CLK-REG builds on Digital Blocks DB-I2C-S-SCL-CLK Controller and additionally supports I2C Master Slave-Transmit and Slave-Receive .
特色
- I3C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
- SCL Clock only for low power, low noise applications requiring configuration & management of User Registers / Memory
- Autonomous I3C Slave Controller:
- No local CPU host required
- No configuring of control/status registers
- Supports I3C SDR up to 12.5 MHz bus speed
- I3C 7-bit Dynamic Address Assignment
- I3C CCC Command Processor
可交付内容
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
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