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I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
The I2C Controller IP Core implements an I2C Slave Controller, with a user parameterized Register Array or Memory (i.e SRAM / FIFO) or any Peripheral connecting on an AHB / APB / AXI / Avalon Bus for embedded user I/O Control & Status or block data transfers within an ASIC / ASSP / FPGA device. The I2C Controller implements the Slave-Transmit and Slave-Receive protocol according to the Philips I2C-Bus Specification, Version 2.1 as well as the NXP Rev .5 October 9, 2012 Specification.
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Block Diagram of the I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
I2C Slave Controller IP
- I2C Master/Slave Controller Core IP
- I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave Controller w/FIFO (APB Bus)
- Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO
- I2C Slave Controller - Low Power, Low Noise Config of User Registers
- I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)