You are here:
HBM2 PHY in TSMC (16nm, 7nm)
The Synopsys DesignWare® HBM2 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking ASIC, ASSP, and system-on-chip (SoC) applications requiring high-bandwidth HBM2 SDRAM interfaces operating at up to 2400 Mbps. The DesignWare HBM2 PHY is ideal for systems with low to modest memory capacity that require higher bandwidth than is attainable with practical DDR4-based systems. The DesignWare HBM2 PHY (Figure 1) is provided as a set of hard macrocells delivered as GDSII. These hard macrocells include integrated applicationspecific HBM2 I/Os required for HBM2 signaling. The design is optimized for high performance, low latency, low area, low power, and ease of integration. The hard macrocells are easily assembled into a complete 512- or 1024-bit HBM2 PHY. The RTL-based PHY Utility Block (PUB) supports the GDSII-based PHY components and includes the PHY training circuitry, configurations registers and BIST control. The HBM2 PHY includes a DFI 4.0-compatible interface to the memory controller, supporting 1:1 and 1:2 clock ratios. The design is compatible with both metalinsulator-metal (MIM) and non-MIM power decoupling strategies.
查看 HBM2 PHY in TSMC (16nm, 7nm) 详细介绍：
- 查看 HBM2 PHY in TSMC (16nm, 7nm) 完整数据手册
- 联系 HBM2 PHY in TSMC (16nm, 7nm) 供应商
Video Demo of the HBM2 PHY in TSMC (16nm, 7nm)
SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.