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HBM2 PHY in TSMC (16nm, 7nm)

The Synopsys DesignWare® HBM2 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking ASIC, ASSP, and system-on-chip (SoC) applications requiring high-bandwidth HBM2 SDRAM interfaces operating at up to 2400 Mbps. The DesignWare HBM2 PHY is ideal for systems with low to modest memory capacity that require higher bandwidth than is attainable with practical DDR4-based systems. The DesignWare HBM2 PHY (Figure 1) is provided as a set of hard macrocells delivered as GDSII. These hard macrocells include integrated applicationspecific HBM2 I/Os required for HBM2 signaling. The design is optimized for high performance, low latency, low area, low power, and ease of integration. The hard macrocells are easily assembled into a complete 512- or 1024-bit HBM2 PHY. The RTL-based PHY Utility Block (PUB) supports the GDSII-based PHY components and includes the PHY training circuitry, configurations registers and BIST control. The HBM2 PHY includes a DFI 4.0-compatible interface to the memory controller, supporting 1:1 and 1:2 clock ratios. The design is compatible with both metalinsulator-metal (MIM) and non-MIM power decoupling strategies.

特色

Complete HBM2 IP solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
DesignWare IP implementation supports data rates up to 2400 Mb/s, which is 20 percent faster than the HBM2 JEDEC standard specification
Pseudo-channel mode doubles the number of channels, resulting in smaller fetch size and higher performance
The HBM2 IP is based on Synopsys’ silicon-proven HBM and DDR4 IP that has been integrated into hundreds of SoC designs
Supports 2.5D-based JEDEC standard HBM2 SDRAMs with data rates up to 2400 Mbps
DFI 4.0-compatible interface
PHY independent training capability
Comprehensive set of design-for-test (DFT) features

优势

Supports 2.5D-based JEDEC standard HBM2 SDRAMs with data rates up to 2400 Mbps
8 or 4 independent memory channels (e.g., 1024 or 512 bits)
Pseudo-channel operation supported to enable up to 16 channels with 1024 bit PHY
Supports up to 4 trained frequencies with <5us switching time
DFI 4.0-compatible controller interface
PHY independent training capability

可交付内容

xecutable .run installation file, including GDSII, LEF Files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample verification environment, PHY data book, physical implementation guide, application notes, verification guide, installation guide, implementation checklist
The PHY Utility Block includes Verilog code, synthesis/STA constraints and scripts, sample verification environment, data book