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Gen-Z Link Layer IP Core
The IntelliProp IPC-GZ198A-ZM Gen-Z Link Layer is an IP Core that allows companies to build Gen-Z compliant devices. The IPC-GZ198A-ZM is compliant with the Gen-Z 1.1 Core specification and provides support for the Link Local protocol and passing of end-to-end packets. The IPC-GZ198A-ZM IP core is designed for integration into FPGA and ASIC developments to minimize development time and familiarization required to develop this IP independently. The IPC-GZ198A-ZM is fully verified in pseudo random simulation.
The IPC-GZ198A-ZM Gen-Z Link Layer IP Core provides a streaming interface to extract and inject end-to-end Gen-Z packets into a Gen-Z fabric. The Link Layer IP Core will consume and produce all Link Local Packets transferred between a peer Gen-Z Link Layer.
The Link Protocol is entirely abstracted away from the user enabling a simpler packet handling scheme in upper layers. All Link sequences including Link initialization, Link Flow Control, Link Synchronization, Transient error detection and handling, etc. are managed autonomously by internal state machines.
The Gen-Z Link Layer IP Core exposes several synthesis time parameters and a memory-mapped register interface for static and dynamic configuration flexibility.
The IPC-GZ198A-ZM Gen-Z Link Layer IP Core provides a streaming interface to extract and inject end-to-end Gen-Z packets into a Gen-Z fabric. The Link Layer IP Core will consume and produce all Link Local Packets transferred between a peer Gen-Z Link Layer.
The Link Protocol is entirely abstracted away from the user enabling a simpler packet handling scheme in upper layers. All Link sequences including Link initialization, Link Flow Control, Link Synchronization, Transient error detection and handling, etc. are managed autonomously by internal state machines.
The Gen-Z Link Layer IP Core exposes several synthesis time parameters and a memory-mapped register interface for static and dynamic configuration flexibility.
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