SweRV Core EL2, Single issue, embedded RISC-V core with 4-stage pipeline
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Embedded OTP (One-Time Programmable) IP, 1.8V/3.3V LP
eMemory's NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated with eNVM. NeoBit embeds seamlessly into a variety of CMOS processes, including logic, mixed-mode, bipolar-CMOS-DMOS (BCD), analog, radio-frequency (RF), and high-voltage (HV).
特色
- Logic Embedded NVM IP
- Programming with channel hot electron injection, erasing with UV illumination
- Testable at wafer level.
优势
- High yield performance
- Small IP size
- Good retention realibility
- Testable at wafer level
- Customization upon request.
可交付内容
- Data Sheet
- Verilog
- Synopsys Model
- GDS Phantom
- Test Methodology
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