The demodulator is designed to be used together with an RF tuner, and an analog to digital converter. The system has an internal state machine to control the operation, and can be externally ...

The FFT/IFFT engine is a parametrized FFT stage used as the main building block for FFT/IFFT/DFT blocks.

Layered implementation. ; Customizable number of iterations. ; Minimum sum algorithm. ; Soft Decision

The FFT/IFFT/DCT engine is an application specific instruction set processor (ASIP) optimized for the implementation of Fourier and cosine transforms, while also supporting general FIR equations. ...

This design is a DVB-T2 OFDM demodulator, supplied as portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. QAM signal constellations ...

The TC4500 Core complies with DVB-T2 specifications. It covers all the FEC and modulation options, including L1 signalling modes. The Core is based on a low complexity architecture, and is available ...

这个功能强大的FEC 子系统基于 LDPC（低密度奇偶校验）码和 BCH（Bose Chaudhuri Hocquenghem）码，允许接近香农极限的准无误操作，专为用于地面广播系统传输的数字视频广播设计。...

这个功能强大的FEC 子系统基于 LDPC（低密度奇偶校验）码和 BCH（Bose Chaudhuri Hocquenghem）码，允许接近香农极限的准无误操作，专为用于卫星数字传输的数字视频广播设计

The DVB-T2/T IP is a silicon-proven IP core extracted from a production chip contains FEC. The DVB-T2 demodulator features microcontroller-assisted operation (embedded) enabling the fast-tracking ...

The Commsonic DVB-T2 Modulator core is intended to provide a very efficient FPGA or ASIC implementation of all functions required to take the output from an MPEG-2 transport multiplexer and ...

LDPC decoder and encoder that supports several standards: ; DVB-S2 ; DVB-T2 ; DVB-C2 ; CMMB ; DMB-T (GB20600-2006) ; Proprietary H-matrices ; ; Versions available for different ...

The DVB-T2 modulator - compliant with ETSI TR 302 755 V1.1.1 standard - is already available for different FPGA supports. Furthermore, it is area-efficient and modular, thus making tailoring ...

The Binary Core DVB-T2 gateway (bc007) is compliant with ETSI TR 302 755 V1.3.1 standard. It can be used to feed multiple DVB-T2 modulators, from Binary Core (bc006) or from third party producers. ...

The DVB-T2 core allows the transmission of an MPEG-TS data stream to a digital to analog converter in base band, IF or RF mode. The core is DVB T2 (ETSI EN 302 755 V1.1.1) compliant and support ...

The fourth generation of the widely licensed Ceva-XC architecture, the Ceva-XC4500 is specifically optimized for next generation wireless infrastructure applications. The Ceva-XC4500 delivers ...

The DVB-C2 Receiver IP Core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder). DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) ...

BCH decoder compliant with the DVB-T2/S2 standard. ; Available for Altera/Xilinx FPGA or ASIC implementation. ; High speed design. ; BCH decoder works on GF(2M) where M = 16 or 14 and correctup ...

The DVB-S2/S Demodulator IP core is a silicon-proven IP core extracted from Production chips. It contains tuner Rx gain control which makes PDM Demodulator a high performance (A)PSK output ...

这是一个单芯片的DVB-T、T2、C、S和S2解调器IP核，已通过硅验证，来自量产芯片组。DVB-T2解调器具有微控制器辅助操作的特点，其特殊设计在于其任何时候都只能处理一个信号（标准）...

Very high throughput (several Gbps) decoder that can be configured on-the-fly as: DVB-S2/S2X LDPC decoder or as Six independent DVB-RCS/RCS2 Turbo decoders

The BCH decoder has four main functional blocks along with memory blocks. Syndrome calculation block calculates syndrome components which tell about presence of errors in the encoded data. Brelekamp ...

DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first ...

The DVB-S2 demodulator IP core performs all tasks of an inner receiver. Its output perfectly fits the DVB-S2 forward error correction IP core that implements LDPC and BCH decoding. DVB-S2 ...

This IP Core is a scalable and programmable co-processor for the signal processing of complex embedded digital signal processing (DSP) systems. This DSP IP Core is a scalable processor architecture ...