Quad core IP platform with integrated Arm security subsystem
The engine is divided into two main parts: a processing element, which deals directly with the data, and an embedded processor to control the signal flow by configuring the processing element. The system architecture is shown in the Fig.
查看 ASIP-2 详细介绍：
- 查看 ASIP-2 完整数据手册
- 联系 ASIP-2 供应商
Block Diagram of the ASIP-2
- 32-kHz Bandwidth Reconfigurable Delta-Sigma ADC providing up to 13 ENOB
- Reconfigurable Parallel CRC Generator
- Low-power high-speed reconfigurable processor to accelerate AI everywhere.
- High Performance Media Processor
- Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
- High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS