ASIP-2
The engine is divided into two main parts: a processing element, which deals directly with the data, and an embedded processor to control the signal flow by configuring the processing element. The system architecture is shown in the Fig.
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Block Diagram of the ASIP-2

Reconfigurable IP
- 12 / 10 / 8-bit Reconfigurable SAR ADC 1.7MS/s (12-bit Mode) 2.8MS/s (8-bit Mode)
- 32-kHz Bandwidth Reconfigurable Delta-Sigma ADC providing up to 13 ENOB
- Reconfigurable Parallel CRC Generator
- Low-power high-speed reconfigurable processor to accelerate AI everywhere.
- High Performance Media Processor
- Partial Reconfiguration AXI Shutdown Manager IP