The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices ...

The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices ...

The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6.1 controller architecture for the CXL.io ...

XpressLINK™是可参数化的Compute Express Link（CXL）控制器软件IP，专为ASIC和FPGA实现而设计。 XpressLINK控制器IP为CXL.io路径应用了PLDA已硅验证的PCIe 5.0 XpressRICH控制器...

XpressLINK-SOC™是可参数化的Compute Express Link（CXL）控制器软IP，专为ASIC和FPGA实现而设计。 XpressLINK-SOC控制器IP为CXL.io路径在PLDA PCIe 5.0 控制器IP基础上(基于PLDA...

Mobiveil’s CXL-Aglx Accelerator platform is a PCIe® Gen5 add-in card with latest Intel’s Agilex I series FPGA. It supports High-Performance Applications, such as Accelerators, Artificial ...

EMPOWER YOUR DESIGN WITH UNMATCHED CXL PERFORMANCE Highly advanced and versatile CXL Controller IP that empowers your design with unparalleled speed, efficiency, and scalability. At Rapid ...

The Alphawave PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Express 6.0 rates (2.5/5/8/16/32/64 GT/s). It ...

The KappaCORE-64 from Alphawave Semi is a CXL™ Controller IP that implements the latest CXL 3.0 spec, which is backward compatible with CXL 2.0 and CXL 1.1 specs. This controller forms a complete ...

Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL cards has same form...

The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be configured for dual-mode applications supporting runtime-selectability ...

DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with minimal impact to latency and badwidth. DenseMem ...

Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Cadence® Controller IP for CXL provides the logic required to integrate an endpoint ...

Cadence 32G NRZ multi-protocol PHY The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 5nm FinFET is a high-performance SerDes operating from 1.25Gbps to 32Gbps and ...

Cadence 32G NRZ multi-protocol PHY The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 7nm FinFET is a high-performance SerDes operating from 1.25Gbps to 32Gbps and ...

Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6.0 for TSMC 5nm delivers a data ...

Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6.0 for Samsung SF5A delivers ...

The CXL Controller IIP core supports the CXL 1.0 and 1.1 Specification. Through its CXL compatibility, it provides a simple interface to a wide range of low-cost devices. CXL Controller IIP ...

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL cards has same form factor as PCIE , and can ...

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL cards has same form factor as PCIE , and can ...

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL cards has same form factor as PCIE , and can ...

Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. An important capability of a Physical ...

Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retimer. An important capability of a Physical ...

The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch. The IP supports all features of the CXL 3.1 specifications and is fully backward ...

Multiprotocol low latency, low power SERDES IP. Support 7nm and 6nm foundry process at leading foundry Available for design in now

Support for multiple protocol PCIE/CXL/Streaming

Gen7 supports 128Gbps and backward compatible with previous versions of PCIE.

The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient ...

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible ...

The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. ...

The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is ...

The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is ...

The AES-GCM Ultra-low latency crypto engine is targeted for CXL link encryption with an implementation of the AES-GCM algorithm compliant with the NIST SP 800-38D standard. The unique architecture ...