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5G/802.11ax MIMO Analog Front-End on TSMC 12nm FFC
The Analog Front End (AFE) is a low-power and low die-area MIMO AFE for Wireless broadband applications such as LTE, 5G, 802.11ax/ Wi-Fi 6E, etc. The AFE can be customizable for numerous MIMO configurations.
The clocks for the ADC and DAC are generated by a versatile low jitter integer mode PLL integrated as part of the AFE.
Also included are auxiliary functions such as Voltage Regulators, Bandgap and Biasing, Low Jitter Clock Tree, Pad Ring etc. Any of these functions can be excluded if desired. The S3AFELTET40 operates from a 0.9V/1.8V supply, and each of the components uses architectures ideally suited for fabrication in 12 or 16nm CMOS process and in complex SoCs.
The AFE does not require any special analog options, and can be cost-effectively ported across foundries, different MIMO configurations and process nodes upon request.
The clocks for the ADC and DAC are generated by a versatile low jitter integer mode PLL integrated as part of the AFE.
Also included are auxiliary functions such as Voltage Regulators, Bandgap and Biasing, Low Jitter Clock Tree, Pad Ring etc. Any of these functions can be excluded if desired. The S3AFELTET40 operates from a 0.9V/1.8V supply, and each of the components uses architectures ideally suited for fabrication in 12 or 16nm CMOS process and in complex SoCs.
The AFE does not require any special analog options, and can be cost-effectively ported across foundries, different MIMO configurations and process nodes upon request.
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Block Diagram of the 5G/802.11ax MIMO Analog Front-End on TSMC 12nm FFC
