The LDO silicon proven in TSMC 90nm is a regulator circuit that features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output while maintaining minimum ripple on supply lines in the presence of large load current spikes inherent with switching loads.
The LDO has been designed to allow low-drop operation in a low area (the PMOS pass device has been scaled for a voltage drop of no more than 600mV). To achieve these goals, the LDO requires a 4.7 uF external ceramic capacitor.
The LDO uses 3.3V thick oxide devices from a standard 90nm logic process. The circuit can be scaled for a range of load currents and the output voltage level is programmable.
For maximum flexibility, the user can adjust the regulated output voltage if the LDO is placed on a different chip.
The LDO is readily portable to any similar manufacturing process or can be customised for specific customer requirements.
- 90nm TSMC CMOS LP, 6 Metals Used
- No Analog Options
- 2.6V – 3.6V Input Voltage
- 1.2V Output Voltage
- 200mA Load Current
- 600mV Drop Out Voltage
- Compact Die Area: 0.11mm2
- Power Down Mode