2.4 Gbps LVDS transmitter

065TSMC_LVDS_07 is LVDS transmitter. The interface to the core logic includes differential signal pins (INP and INN) to transmit data, and control pin EN to configure the state of the transmitter. EN pin enables of the TX LVDS, OEN pin selects Hi-Z state mode in which the output is disconnected. There are other two internal pins (VREF and IREF) to get voltage reference and current reference. OUTP and OUTN are complementary outputs to connect to the bonding pads.

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