The S3AD5M14BC18 is an ultra-low-power and ultra-low area 14-bit sigma-delta (SD) ADC IP operating up to 5.5MS/s and dissipating only 200uW (ADC core) over a 0.9V supply. The measured dynamic range is about 82dB for an input signal bandwidth of 10kHz.
The digital filters are not included in the IP core (e.g. decimation filter and programmable low-pass/band-pass filter).
Dynamic performance highlights considering an input signal with 2.5kHz frequency and 5MS/s sampling rate (OSR=256) include an SNR of 81dB, SNDR of 78dB and DR of 82dB.
Auxiliary circuits comprising a low-noise bandgap reference and voltage reference buffers are also included to provide a complete ADC solution. Moreover, a dedicated cascaded DFLP/BP digital filter can be designed for each specific application.
- 0.18um UMC MM 1P6M Process 1.8V core, 3.3V I/Os
- 14-bit 10kHz Signal Bandwidth Delta-Sigma ADC
- Sampling Rate Up to 5.5MS/s
- Conversion Rate Up to 20 kS/s
- Single 1.2V Supply (–25% tolerance down to 0.9V)
- 1.0Vpp Differential Input Range
- 200uW Power Dissipation at 5MS/s and 0.9V Supply (ADC core)
- SNR= 81dB at FIN= 2.5kHz, –6dBV Input and 5MS/s
- SFDR= 90dB at FIN= 2.5kHz,–6dBV Input and 5MS/s
- SNDR= 78dB at FIN= 2.5kHz,–6dBV Input and 5MS/s
- DR= 82dB at FIN= 2.5kHz, –6dBV Input and 5MS/s
- 12.6-bit ENOB at FIN= 2.5kHz,–6dBV Input and 5MS/s
- Optional Internal Voltage References
- Ultra Compact Die Area