The S3ADSD3M14BT40LP is a highly-compact and ultra-low power Continuous-Time Sigma-Delta ADC with an input Signal Bandwidth of 1.4MHz.
This IP includes a first-order Anti-Aliasing filtering function. Noise Shaping is implemented with a 3rd Order Modulator. Working at 200MHz clock frequency, this ADC features an outstanding performance that includes 75.0dB Dynamic Range, 68.5dB SNR and 11.0-bit ENOB.
To allow for application flexibility whilst offering minimum area and power dissipation, this IP does not include the Digital Decimation Filter. If required, it can be included in the IP or it can, otherwise, be included externally in the SoC DSP.
- TSMC 40nm LP Process
- No Analog Options
- 1.1V Supply Voltage
- Continuous-Time Sigma-Delta ADC
- Built-In 1st Order Anti-Aliasing Filter
- 1.4MHz Input Signal Bandwidth
- 200MHz Output Bitstream
- 200MHz Input Clock Frequency
- Input Signal Range: 1.0Vppdiff
- Outstanding Performance:
- 75.0dB Dynamic Range
- 68.5dB SNR
- 68.0dB SNDR
- 11.0-bit ENOB
- Ultra Low Power Dissipation: 300uW
- Highly Compact Die Area: 0.02mm2
- (Decimation Filter not included)
- Excluding the Digital Decimation filter, this ADC power dissipation is only 300uW and occupies only 0.02mm2 area.
- The S3ADSD3M14BT40LP does not require any special analog process options.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog)
- Integration Support
- Wireless Communications: LTE-M
- Wireline Communication Networks
Block Diagram of the 来自于S3 Group应用于LTE-M等无线及有线通信的Continuous-Time Sigma-Delta ADC。