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Ultra-Low Power 6 - 13 Bit 0.5 -10 kS/s 10μW Analog Front End
The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique. The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s). The preamplifier offers programmable gain from 0.5 to 4. The input voltage range is quasi-rail-to-rail guaranteeing more than +- 1.7 V @ 1.8 V power supply. An optional calibration technique can be applied to compensate degraded mismatch behavior of t echnology capacitors. The overall power consumption of the AFE IP sums up with 10.5 μW at 1 kHz input signal.
The AFE ASIC with current and voltage input channels was applied to commercial environmental sensors for ambient light, temperature and CO gas. An internal temperature monitor is included.
The AFE ASIC as well as the stand-alone SAR ADC are silicon evaluated using the XFAB XT018 process. Measurement results and samples are available.
The AFE IP was migrated to GF 22FDX. Fraunhofer IIS/EAS provides a detailed documentation and support for the IP integration. Modifications, extensions and technology ports of the IP are available on request.
The AFE ASIC with current and voltage input channels was applied to commercial environmental sensors for ambient light, temperature and CO gas. An internal temperature monitor is included.
The AFE ASIC as well as the stand-alone SAR ADC are silicon evaluated using the XFAB XT018 process. Measurement results and samples are available.
The AFE IP was migrated to GF 22FDX. Fraunhofer IIS/EAS provides a detailed documentation and support for the IP integration. Modifications, extensions and technology ports of the IP are available on request.
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Block Diagram of the Ultra-Low Power 6 - 13 Bit 0.5 -10 kS/s 10μW Analog Front End
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