12Bit 424M采样率ADC，应用于下一代DSL/有线通信/无线通信/图像处理等。

特色

• TSMC 40nm Low Power Process (LP)
• No Analog Options
• 1.1V Core & 2.5V I/O Supplies
• 12-bit High-Speed SAR ADC
• 424MS/s Sampling Rate
• Input Clock CLK: 424MHz
• Internal Bandgap and Biasing System Included
• All required Voltage References Included
• No External Accurate Reference required
• No External Reference Decoupling required
• Good Power-Supply Noise Rejection
• Differential Input Signal Range: 1.0Vppdiff
• Outstanding Dynamic Performance:
• 76.0dB SFDR
• -75.0dB THD
• 63.5dB SNR
• 63.1dB SNDR o 10.2-bit ENOB
• [Noise integrated up-to Nyquist]
• Idle-Mode and Power-Down Modes
• Ultra Low Power Dissipation: Only 42mW (complete ADC incl. References)
• Ultra Compact Die Area: Only 0.21mm2

优势

• This high-end performance is obtained while dissipating a mere 42mW for the complete ADC, including internal references.
• The S3ADS424M12BT40LPB does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.

可交付内容

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioral Model (Verilog)
• Integration Support

应用

• Next Generation DSL
• Wireline Communications
• Wireless Communications Infrastructure
• Imaging

Block Diagram of the 12Bit 424M采样率ADC，应用于下一代DSL/有线通信/无线通信/图像处理等。

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