This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes internal sample/hold circuits, a capacitive DAC, a comparator, and logic control circuits. External reference voltage is needed. The voltage reference input can be adjusted to allow encoding from smaller analog voltage span to the full 12 bits of resolution. This ADC has dual operation modes, i.e. single-ended and differential-ended. Differential-ended mode is used in high-speed and noisy environment; Single-ended mode is used in low-speed and clean environment. This ADC has dual speed modes, i.e., high speed and low speed, working in low speed mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power. The converter has flexible control logic, and could be easily embedded in a big system. The IP is suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.
- Process: IBM 65nm 2.5/1.2V (CMOS 10LPE)
- Resolution: 12-bit resolution
- DNL: +/-1.5 LSB, INL: +/-3 LSB
- Analog input range: VREFL to VREFH, could be rail-to-rail
- Analog supply: 2.25 - 2.75V; Digital supply: 1.08 – 1.32V
- Single-ended / differential analog input
- Dual data rates: 1MSPS/200KSPS
- Auto power down mode: < 10uA
- Low power: < 3200μW(@1MSPS) / < 1000μW(@200kSPS)
- Flexible control logic: to be easily embedded in a system, or operates “stand alone".
- Operating junction temperature: -40~1250C