10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
12b 5Msps ADC for microcontroller business in UMC 40nm
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A/D IP
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- ARC Functional Safety (FS) Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive SoC development and accelerate ISO 26262 qualification
- 2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- 2D/3D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- JESD204D
- 3D OpenGL ES 1.1 GPU (Graphics Processing Unit)