The S3ADS100M12BSM55LL is an ultra low-power, ultracompact 12-bit High-Speed SAR ADC IP.
This ADC sampling at 100MS/s features an excellent dynamic performance including -75.0dB THD, 63.5dB SNR and 10.2-bit ENOB (noise integrated up-to Nyquist bandwidth, including References circuitry noise contribution).
This high-end performance is obtained with an ultra compact die area of 0.1mm2 and dissipating a mere 13mW for the complete IP.
- SMIC 55nm LL Process (Low Leakage)
- No Analog Options
- 1.2V Core & 2.5V I/O Supplies
- 12-bit High-Speed SAR ADC
- 100MS/s Sampling Rate
- Internal Bandgap and Voltage Ref. Buffer Included
- No External Accurate Reference required
- No External Reference Decoupling required
- Differential Input Signal Range: 1.0Vppdiff
- Outstanding Dynamic Performance:
- 76.0dB SFDR
- -75.0dB THD
- 63.5dB SNR
- 63.1dB SNDR
- 10.2-bit ENOB
- [Noise integrated up-to Nyquist]
- Low Power Dissipation: 13mW
- Compact Die Area: 0.1mm2
- The S3ADS100M12BSM55LL does not require any special analog options and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- Connected Consumer Devices
- Wireless & Wireline Communications
Block Diagram of the 12-bit 100MS/s High-Speed SAR ADC