The AHA4502D Turbo Product Code decoder IP core is intended for both FPGA based and ASIC based products. The core is configurable allowing a broad range of code rates and correction power. Data interfaces consist of one soft metric per clock into the decoder and one-bit serial out of the decoder, and both input and output data interfaces use a synchronous handshake transfer protocol. The core design uses one clock, rising edge only. Number of iterations can be constant or variable allowing the device to stop iterating early if no more iterations are required. Status output allows monitoring of correction performance.