The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane Ethernet) standard draft for 100GBASE-CR4 and 100GBASE-KR4 PHY. The encoder and decoder functions are completely independent and packaged as two sub-cores, RS100-160E and RS100-160D respectively. Decoder corrects up to 7 word errors; an option supporting RS(544, 514) for 100GBASE-KP4 PHY (correcting up to 15 errors) is also available .
The RS100-160E core implements the FEC encoder per section 188.8.131.52 of the IEEE 802.3bj draft standard. The core accepts sixteen 10-bit words (160 bit total) on every clock and outputs the encoded result 3 clocks later.
The RS100-160D core implements the FEC decoder per section 184.108.40.206 of the IEEE 802.3bj standard. It accepts sixteen 10-bit words (198 bit total) on every clock and outputs the decoded result 49 clocks later.
- Implements FEC Sublayer for 100GBASE-CR4 and 100GBASE-KR4 PHY (clause 91 of the IEEE 802.3bj standard) 100G Ethernet MAC-friendly interface.
- Core features include:
- 160-bit parallel interface
- Optional automatic FEC block boundary lock on decoding
- Self-contained, requires no external memory. A reduced gate count version with a small external RAM is available.
- Flow-through design; low latency
- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Test vectors
- Expected results
- User Documentation
- 100GBASE-CR4 and 100GBASE-KR4 PHY