The S3DA50M10BT55ULP employs a current steering architecture with differential current outputs. It uses 5 linear bits and 5 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist
- 55nm TSMC ULP eFlash Process, 7 Metals Used (No Analog Options)
- 2.5V and 1.2V Supplies
- Sampling Rate up to 50MS/s
- 2.0Vpp Differential Output Range
- DNL< 0.5LSB Typ.; INL< 1.0LSB Typ
- Output current range 4-20mA
- Performance at 50MS/s
- SNR >61dB, SFDR > 62dBc, FOUT = 1MHz
- Stand-By and Power-Down Modes
- Area Pre-shrink Area: 0.1mm2
- The 10-bit DAC dynamic performance highlights considering a signal frequency of 1MHz and 50MS/s conversion rate include an SNR > 61dB and an SFDR > 62dBc.
- The S3DA50M10BT55ULP is designed in a 55nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- Subject to Agreement
Block Diagram of the 10-Bit 50MS/s Current Steering DAC