This IP is a triple channel 10-bits 10 MS/s general purpose voltage output DAC, optimized for analog LCD controller application and designed for industry standard 0.18um 1P6M CMOS technology supplied at 3.3V.
Each independent DAC uses an internal segmented current steering architecture, with at least 10-bit of intrinsic static accuracy, combined with an high slewrate (120V/uS), and high output current (up to 36mA), rail to rail voltage output driver.
A 1V full scale option allow the DAC to also deliver standard video signals on a 37.5Ω termination.
- Programmable full scale : 3V or 1V.
- 10 Bits resolution.
- 10MS/s update rate.
- Adjustable max output current 24, 30 or 36mA.
- 3.3V ±10% supply voltage, -40/+125°C temperature.
- 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
- Individual DAC channel Power down.
- Do not require extra external bias circuit.
- Cell area: [contact us]
- Design Kit includes:
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available
- Tapeout kit includes the design kit plus plysical view:
- LVS netlist and report
- DRC/ERC/ESD/ANT report