UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
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VESA DSC V1.2 Decoder
Arasan’s VESA DSC v1.2 decoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel in RGB or YCbCr format (4:4:4 or 4:2:2). The DSC Encoder core is industry-standard in its integration of host setup and control, data input, and visual output. Arasan’s VESA DSC decoder IP is seamlessly integrated with Arasan’s DSI Rx IP. Arasan’s expertise is backed by our unique silicon-proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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Block Diagram of the VESA DSC V1.2 Decoder
dsc IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
- VESA DSC 1.2b Encoder for Xilinx FPGAs
- VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs