MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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VESA DisplayPort 2.0 FEC RX
The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 2.0 specification. Forward Error Correction is required to ensure low bit error rate at UHBR link rates and glitch-free Display Stream Compression (DSC) bitstream transport.
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Block Diagram of the VESA DisplayPort 2.0 FEC RX
DisplayPort IP
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