MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.
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Block Diagram of the VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
