PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
USB2.0 PHY_TSMC
The INNO USB 2.0 PHY is capable to handle the low-level protocol and signaling. In transmitting mode, the PHY serializes data, performs bit stuffing following NRZI encoding when needed, and then generates SYNC and EOP fields. Likewise, in receiving mode, it recovers clock from incoming data, strips the SYNC and EOP fields, performs NRZI decoding with bit un-stuffing when needed and then de-serializes the data. It supports17 modes of operations, including LS, FS, HS, and Device and Host.
The INNO USB 2.0 PHY can be pre-configured as a 30MHz 16-bit or 60MHz 8-bit UTMI data interface, which provides a complete on-chip transceiver physical solution with ESD protection.
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USB2.0 PHY IP
- USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
- USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
- USB2.0 Host Transceiver PHY
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- IBM 65nm USB2.0 Dual Role PHY
- SMIC 65nm USB2.0 Dual Role PHY