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USB 2.0 PHY
The USB 2.0 PHY is a complete mixed-signal IP solution designed to implement OTG connectivity in a System-on-Chip (SoC) design targeted to a specific fabrication process using core and 2.5-V thick-oxide devices. The USB 2.0PHY supports the USB 2.0 480-Mbps protocol and data rate and is backward compatible with the USB 1.1 1.5-Mbps and 12-Mbps protocol and data rates.
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USB 2.0 IP
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
- USB 2.0 nanoPHY in SMIC (65nm)
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 22ULP
- USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP