Based on UMC 0.18um 3.3v/1.8v Logic Process, current design of Power Regulator is to provide the 3.3v voltage output regulated from a 5v input supply. Moreover, the design is resilient against any reliability issue. The maximum output current is 250mA. This IP also supports bypass mode when AVDD and AVDD5 are 3.3v input. It can be forced by setting BYPASS=AVDD or can be detected automatically by internal sensor (When BYPASS=0). The internal voltage detector can check the V33 output. When V33 rises to trigger point, FLGH and FLGL will output high.