MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
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UltraScale Gen3 Integrated Block for PCI Express (PCIe)
Xilinx provides a PCI Express Gen3 Integrated block for PCI Express® (PCIe) in the UltraScale™ family of FPGAs. The UltraScale FPGA solution for PCI Express Gen3 includes all of the necessary components to create a complete solution for PCIe. Delivered through Vivado®, the Xilinx IP for Endpoint and Root Port simplifies the design process and reduces time-to-market.
This core combined with Xilinx Targeted Design Platforms, helps customers develop system solutions.
This core combined with Xilinx Targeted Design Platforms, helps customers develop system solutions.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC