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Ultimate Performance for Next-Generation Smartphones and Laptops
The Cortex-X4 core is a high-performance and low-power product that implements the Arm®v9.2-A architecture. The Arm®v9.2-A architecture extends the architecture defined in the Arm®v8‑A architectures up to Arm®v8.7‑A.
The Cortex-X4 core is implemented inside a DSU-120 DynamIQ™ cluster. It is connected to the DynamIQ Shared Unit-120 that behaves as a full interconnect with L3 cache and snoop control. This connection configuration is also used in systems with different types of cores where the Cortex-X4 core is the high-performance core.
The following figure shows an example configuration with four Cortex-X4 cores in a DynamIQ™ cluster.
The Cortex-X4 core is implemented inside a DSU-120 DynamIQ™ cluster. It is connected to the DynamIQ Shared Unit-120 that behaves as a full interconnect with L3 cache and snoop control. This connection configuration is also used in systems with different types of cores where the Cortex-X4 core is the high-performance core.
The following figure shows an example configuration with four Cortex-X4 cores in a DynamIQ™ cluster.
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Arm Cortex-X4 IP
- InCore Calcite Series: 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- InCore Azurite Series: 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- Quad core IP platform with integrated Arm security subsystem
- ARM HSSTP PHY with Link Layer
- SPI Master / Slave Controller w/FIFO (APB Bus)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)