This macro is a triple-channel, 8/10-bits video analog front end (AFE) that incorporates all of the functions required to digitize High Definition YpbPr/YUV (component) video signals and RGB (red, green, blue) graphic signals from DVD players, VCRs, set-top boxes and personal computers.
It contains all the video and timing pre-processing circuits, offset control, gain control, bottom and midscale clamping, SOG slicer, VSYNC/HSYNC extractor, 32 phases clock shift control , internal or external clamp and coast signals generation, as well as an analog pixel clock PLL with optimized long term jitter <500ps.
This IP is fully programmable through 2 wires I2C interface.
- Triple channel video 10bits digitizer 170Mhz
- 0.5 to 1V analog input range
- 3.3V/1.8V ±10% supply voltage, -40/+125°C
- 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
- Analog PLL with 32 phases shift control
- Adjustable bandwidth : 75, 150, 300, 500Mhz
- Programmable Clamp and Coast generation
- Area: [contact us]
- Power consumption - (contact us) mW at 170MS/s; (*) mW at 205MS/s
- Power down leakage current <1uA
- Fully programmable through I2C interface
- Antenna diodes on each digital input.
- uses MIM capacitor
- low cost
- very easy to integrate
- full support
- possible customization to match your needs
- Design Kit includes:
- LEF view and abstract gdsII
- Verilog HDL behavioral model
- Liberty (.lib) timing constraints for typical, worse and best corner case
- Full Datasheet /Application Note with integration guidelines document
- Silicon characterization report when available
- Tapeout kit includes the design kit plus plysical view:
- LVS netlist and report
- DRC/ERC/ESD/ANT report