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The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications
The Synopsys 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet providing a simple frame-based interface to the system and a standardized interface to the PCS (Physical Control Block).
The Synopsys IP is split into four 400Gbps channels which can be configured via software-controllable registers to operate together to support higher data rates. The MAC supports the following data-rates:
400 Gbps with up to four independent ports active simultaneously
800 Gbps with up to two 800 Gbps ports or one 800 Gbps and two 400Gbps ports active simultaneously
1600 Gbps as a single port
The application interface is a FIFO-based interface with four channels capable of transferring up to 4x512-bits of frame data per clock cycle and per direction. The PCS interface consists of four channels 320-bit wide each, encoded according to IEEE 802.3 Clause 117 (400GMII) and clock-synchronous to the corresponding PCS interfaces. The rate is controlled via per-channel PCS-driven data-enable signals for both transmit and receive directions.
The Synopsys 1.6T Ethernet MAC IP seamlessly interoperates with Synopsys 1.6T Ethernet PCS IP and Synopsys 224G Ethernet PHY IP to provide a complete Ethernet MAC, PCS and PHY solution for 1.6T systems.
The Synopsys IP is split into four 400Gbps channels which can be configured via software-controllable registers to operate together to support higher data rates. The MAC supports the following data-rates:
400 Gbps with up to four independent ports active simultaneously
800 Gbps with up to two 800 Gbps ports or one 800 Gbps and two 400Gbps ports active simultaneously
1600 Gbps as a single port
The application interface is a FIFO-based interface with four channels capable of transferring up to 4x512-bits of frame data per clock cycle and per direction. The PCS interface consists of four channels 320-bit wide each, encoded according to IEEE 802.3 Clause 117 (400GMII) and clock-synchronous to the corresponding PCS interfaces. The rate is controlled via per-channel PCS-driven data-enable signals for both transmit and receive directions.
The Synopsys 1.6T Ethernet MAC IP seamlessly interoperates with Synopsys 1.6T Ethernet PCS IP and Synopsys 224G Ethernet PHY IP to provide a complete Ethernet MAC, PCS and PHY solution for 1.6T systems.
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