You are here:
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.
The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process.
查看 The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process. 详细介绍：
- 查看 The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process. 完整数据手册
- 联系 The PLL is design with UMC 0.11um AE process, with input frequency from 8MHz to 100MHz,and output frequency from 60MHz to 480MHz according to the user setting. UMC 0.11um AE process. 供应商
Analog IP
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Analog I/O - low capacitance, low leakage
- Bluetooth Low Energy (BLE) analog PHY
- Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO