MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
TCAM in SMIC 28HK+ upto 800Mbps
特色
- High yield: In-house developed Bit Cell, matching logic design rule.
- High reliability: Logic bit cell design, avoid process violation.
- Low power design: Hierarchical search line and hierarchical matching line.
- High performance: Optimized PPA with full custom design.
- High speed: Working speed supports 1GHz.
- High flexible design: Memory compiler design.
- High density: Memory compiler supports maximum 1K x 160bits.
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TCAM IP
- TSMC CLN16FFC TCAM Compiler with ULVT periphery
- UMC 40nm LP process standard synchronous high density TCAM memory compiler.
- UMC 40nm LP Logic Process TCAM with LVT peripheral memory compiler
- UMC 28HPC process standard synchronous high density TCAM memory compiler
- Low Power TCAM depth 1K and width upto 280
- eTCAM (Embedded Ternary Content Addressable Memory IP