MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors
Superscalar Out-of-Order Execution Multicore Cluster
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Block Diagram of the Superscalar Out-of-Order Execution Multicore Cluster

RISC-V; superscalar;dual-issue;8-stage pipeline;microprocessor;64-bit IP
- 64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN
- 64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
- 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension