MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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Standard Cell (Generic) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process metal programmable (M3/M4/M5) cell array standard Core Cell Library.
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