MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
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Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process 2.5V/3.3V SSTL2 Class II/LVTTL combo IO with POC (Pad On Circuit).
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