MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E)
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Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe)
Version 1.8 Now Supports Spartan™-3/3E/3A
The Xilinx Spartan-3 LogiCORE™ Endpoint PIPE for PCI Express® (PCIe®) protocol layer core is available for Xilinx low-cost 90nm Spartan-3/3E/3A families. PCIe is a high-speed duplex serial interface standard supported by many industry leaders. The PCIe PIPE Endpoint LogiCORE combined with a discrete PCIe PHY offers a complete PCIe Endpoint solution fully compliant to the PCI Express Base Specification v1.1.
The Xilinx Spartan-3 LogiCORE™ Endpoint PIPE for PCI Express® (PCIe®) protocol layer core is available for Xilinx low-cost 90nm Spartan-3/3E/3A families. PCIe is a high-speed duplex serial interface standard supported by many industry leaders. The PCIe PIPE Endpoint LogiCORE combined with a discrete PCIe PHY offers a complete PCIe Endpoint solution fully compliant to the PCI Express Base Specification v1.1.
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Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC