HEVC/AVC Single-core Video Encoder HW IP of Low-cost Version: 4K60fps
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SMIC 65nm Low Leakage LVDS Receiver
The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core that can support Single-Link transmission with up to SXGA+ resolution, or Dual-Link transmission with up to UXGA resolution. This IP is suitable for Flat Panel Display applications.
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SMIC 65nm Low Leakage LVDS Receiver IP
- FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz
- FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability
- Dual FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @120Hz) LVDS SerDes 10:70 channel decompression with deskew capability