7 track Ultra High Density standard cell library at TSMC 28 nm
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Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
The CEVA-BX2 audio/voice DSP is targeted for high performance audio devices such as DTV, Smart Speaker, Soundbar, and car infotainment systems.
CEVA-BX2 uses quad 32X32-bit MACs and octal 16X16-bit MACs, with enhanced capability for supporting 16×8-bit and 8×8-bit MAC operations.
The CEVA-BX2 is using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at a TSMC 7nm process node.
The CEVA-BX2 Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) as well as optional floating point units for high accuracy algorithms.
The CEVA-BX2 is accompanied by a comprehensive software development tool chain, including:
* Advanced LLVM compiler
* Eclipse based debugger
* DSP and neural network compute libraries
* Neural network frameworks support
* Real Time Operating Systems (RTOS)
CEVA-BX2 uses quad 32X32-bit MACs and octal 16X16-bit MACs, with enhanced capability for supporting 16×8-bit and 8×8-bit MAC operations.
The CEVA-BX2 is using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at a TSMC 7nm process node.
The CEVA-BX2 Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) as well as optional floating point units for high accuracy algorithms.
The CEVA-BX2 is accompanied by a comprehensive software development tool chain, including:
* Advanced LLVM compiler
* Eclipse based debugger
* DSP and neural network compute libraries
* Neural network frameworks support
* Real Time Operating Systems (RTOS)
特色
- Octal 16x16 MACs
- Quad 32x32 MACs
- 5-way VLIW
- 8/16/32/64-bit data types
- 16x8 and 8x8 Neural Network support
- Half and single precision IEEE floating point units
- Innovative Branch Target Buffer minimizing branch overhead
- Hardware loop buffer for reduced power consumption of code loops
- High performance controller
- 5 CoreMark/MHz
- Dynamic branch prediction
- Full RTOS support
- Compact code size
- Advance system control
- Automatic Queue and Buffer management mechanisms to integrate co-processors and create a cluster of CEVA-BX cores
- Dedicated HW accelerator ports
优势
- Up to 16 GMAC/sec tailored for sound neural networks
- High-throughput DSP addresses advanced applications
- CEVA-Connect offloads the processor from data transfers to hardware accelerators and peripherals
Block Diagram of the Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
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