This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 200MHz to 500MHz. It contains a 1-64 input clock divider (DM), a 1-128 feedback clock divider (DN), a 1-8 output clock divider (DP) and a fraction control block (FRAC). It can work either in Integer Mode or in Fraction Mode. By setting DM, DN, DP and FRAC to different values, the output clock will be locked at different multiples of the input frequency. A lock indicator is also included in this PLL. Its output shows whether the output clock is at the right multiples of the input clock.
- Process: SMIC 0.13um Logic 1P8M 1.2v/3.3v CMOS process
- Supply voltage: 1.2v±10%
- Current: <5mA
- Operating temperature: - 40°C ~ +25°C ~ +125°C
- Two outputs: - PLL_CLKO: standard output from the output divider - PLL_CLK: output from mux
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