You are here:
Small, Low Power, Energy Efficient 32-bit Microcontroller Processor
The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices.
The ultra-low gate count of the Cortex-M0 processor also enables its deployment in analog and mixed signal devices. Arm DesignStart™ provides free and instant access to the industry-leading Cortex-M0 and Cortex-M3 processors and related system IP. Anyone can evaluate Arm IP with DesignStart Eval with a simple click-through access; or, companies can get a commercial license for a $0 upfront fee, just a success-based royalty model, by registering for DesignStart Pro. It’s the fastest, simplest, no-risk route to custom silicon success.
The ultra-low gate count of the Cortex-M0 processor also enables its deployment in analog and mixed signal devices. Arm DesignStart™ provides free and instant access to the industry-leading Cortex-M0 and Cortex-M3 processors and related system IP. Anyone can evaluate Arm IP with DesignStart Eval with a simple click-through access; or, companies can get a commercial license for a $0 upfront fee, just a success-based royalty model, by registering for DesignStart Pro. It’s the fastest, simplest, no-risk route to custom silicon success.
查看 Small, Low Power, Energy Efficient 32-bit Microcontroller Processor 详细介绍：
- 查看 Small, Low Power, Energy Efficient 32-bit Microcontroller Processor 完整数据手册
- 联系 Small, Low Power, Energy Efficient 32-bit Microcontroller Processor 供应商
Block Diagram of the Small, Low Power, Energy Efficient 32-bit Microcontroller Processor
ARM IP
- InCore Calcite Series: 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- InCore Azurite Series: 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- Quad core IP platform with integrated Arm security subsystem
- ARM HSSTP PHY with Link Layer
- SPI Master / Slave Controller w/FIFO (APB Bus)
- eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)