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Single precision, IEEE 754, floating point multiplier
The eSi-SP-FP-Multiplier IP core implements single-precision (32-bit), IEEE 754 compliant, floating-point multiplication.
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IEEE 754 IP
- Single precision, IEEE 754, floating point adder
- Single precision, IEEE 754, floating point divider
- IEEE 754 Floating Point Coprocessor
- Single precision floating-point fast speed parametrized multi operands adder
- Single precision floating-point 2 cycle's multiplier
- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs